FYI @kgugala this works nicely on HPS, and gives a reduction in resource usage. But I confirmed this only reduces model evaluation time by ~0.35%.

FYI @kgugala this works nicely on HPS, and gives a reduction in resource usage. But I confirmed this only reduces model evaluation time by ~0.35%.

is this with picolibc and LTO?

Yes, these are the numbers I have in my spreadsheet running on HPS proto2 board, evaluating HPS model.

commit 10400f2 (last week)
= 193473536 cycles

commit 740150c (current main)
= 176910336 cycles

this PR
= 176288768 cycles

It suggests picolibc and LTO give a good speed improvement, as you reported, but effectively no change from doubling the SPI flash clock. It doesn't seem right.

maybe to biggest bottleneck is not in flash now?

@danc86, @kgugala: I'd like to merge litex-hub/litespi#60 that simplifies DDR mode but need feedback (I was only able to test on Arty), could you do a test with it? Thanks.

@danc86, @kgugala: I'd like to merge litex-hub/litespi#60 that simplifies DDR mode but need feedback (I was only able to test on Arty), could you do a test with it? Thanks.

I tried with that PR applied and it doesn't work (CPU never boots from SPI flash). I haven't looked closer at why not. I'll write a comment with more details on that Litespi PR.

I want to do more investigation on this (including to understand why there is no effective difference in model evaluation time) but I think we should merge it now and continue from here.